1. Field of the Invention
The present invention relates to CMOS output buffers, and more particularly, to a high voltage CMOS output buffer that is constructed from low voltage CMOS transistors.
2. Description of the Related Art
CMOS processing rules are being continually scaled downward, producing smaller and faster transistors that have shorter channel lengths and lower threshold voltages. CMOS device scaling also offers other important advantages, including shorter interconnect wires that have lower capacitance, and the use of lower VDD voltages.
The use of lower VDD voltages is extremely important, because it significantly decreases PWRDIG, the digital power dissipation inside the core of a CMOS chip. The formula for calculating PWRDIG is shown in EQ. 1.PWRDIG=C*VDDINT2*F  EQ. 1where C represents the average gate plus interconnect capacitance, VDDINT represents the internal (digital core) power supply voltage, and F represents the average operating frequency of the logic gates inside the digital core.
Referring to EQ. 1, it can be seen that CMOS device scaling reduces PWRDIG in two ways. First of all, it lowers PWRDIG by lowering the average gate plus interconnect capacitance C. Secondly, it again lowers PWRDIG by allowing a lower VDDINT voltage to be employed. Of course, because PWRDIG depends upon the square of VDDINT, lowering VDDINT makes the largest contribution to decreasing the power dissipation inside the digital core of a chip.
Furthermore, since CMOS device scaling has been progressing at a very rapid rate, VDDINT has also been decreasing at a very rapid rate. For example, in recent years, VDDINT has progressed from 5V to 3.3V, from 3.3V to 2.5V, from 2.5V to 1V—and even lower.
A basic problem, however, is that the standard system power supply voltage VDDSYS has been decreasing at a much slower rate than VDDINT. For example, in current systems, the most widely used VDDSYS voltages are still 5V and 3.3V. Because of this VDD disparity, CMOS I/O buffers must operate from the higher VDDSYS voltage, while the CMOS logic gates inside the digital core must operate from the lower VDDINT voltage.
With regard to CMOS output buffers, the above VDD disparity can be resolved in two ways. In a first approach, only the system power supply voltage VDDSYS is distributed to a CMOS chip. This approach is illustrated in FIG. 1A, which shows a block diagram of a prior-art CMOS chip 100. As shown in FIG. 1A, since CMOS chip 100 only receives the system power supply voltage VDDSYS, CMOS chip 100 must contain an on-chip voltage regulator 110.
In this example, voltage regulator 110 is used to reduce the system power supply voltage VDDSYS to the lower internal power supply voltage VDDINT. Furthermore, the internal power supply voltage VDDINT is fed to a digital core 112, which only contains low voltage CMOS transistors. In addition, the system power supply voltage VDDSYS is also fed to an output buffer block 114. Moreover, VDDSYS and VDDINT are both fed to a level shift-down block 116, and to a level shift-up block 118. As shown in FIG. 1A, these level shift blocks act as voltage translators for the signals that go to and from digital core 112.
In a second approach, the higher system power supply voltage VDDSYS and the lower internal power supply voltage VDDINT are both distributed to a CMOS chip. This approach is illustrated in FIG. 1B, which shows a block diagram of a prior-art CMOS chip 150. As shown in FIG. 1B, CMOS chip 150 receives the system power supply voltage VDDSYS and the internal power supply voltage VDDINT. Therefore, CMOS chip 150 does not need an on-chip voltage regulator. In this example, the internal power supply voltage VDDINT is directly fed to a digital core 152, and the system power supply voltage VDDSYS is directly fed to an output buffer block 154. Furthermore, the VDDSYS and VDDINT voltages are both fed to a level shift-down block 156, and to a level shift-up block 158.
The two approaches described above both require that the CMOS output buffers 114/154 operate from the higher VDDSYS voltage. Thus, using prior art, this requirement is often satisfied by employing two transistor types: low voltage (low threshold) PMOS/NMOS transistors operating from VDDINT, and high voltage (high threshold) PMOS/NMOS transistors operating from VDDSYS. Referring to FIGS. 1A and 1B, the low voltage transistors are used inside the digital core 112/152, and the high voltage transistors are used inside the I/O cells 114/154.
Of course, fabricating low voltage CMOS transistors and high voltage CMOS transistors on the same chip increases CMOS processing complexity, which increases chip fabrication cost. Therefore, if the high voltage transistors could be eliminated, the chip fabrication cost could be substantially reduced.
Furthermore, if the high voltage transistors could be eliminated, shift-up blocks 118/158 and shift-down blocks 116/156 could also be eliminated, further reducing the chip fabrication cost. Therefore, there is an obvious need for a method of implementing high voltage CMOS output buffers using only low voltage CMOS transistors. Two examples of this need include the ability to implement 5V output buffers using 3.3V transistors, and the ability to implement 3.3V output buffers using 2.5V transistors.
CMOS transistors have four terminals: a gate terminal, a drain terminal, a source terminal, and a body (or substrate) terminal. In most CMOS processes, the NMOS transistors are not fabricated inside of wells. Therefore, the bodies of the NMOS transistors are formed by the p-substrate, which is usually grounded.
Furthermore, in all CMOS processes, the PMOS transistors are always fabricated inside of N-wells, and the bodies of the PMOS transistors are formed by these N-wells. Thus, in order to avoid forward biasing the PMOS source/drain diodes, the PMOS N-wells are usually connected to the most positive voltage available, VDD. Since this connection is not mandatory, it is often permissible to connect the body (N-well) of a PMOS transistor to its own source terminal.
FIGS. 2A-2B show schematic diagrams that illustrate a prior-art PMOS transistor 200, and a prior-art NMOS transistor 250. As shown in FIGS. 2A-2B, both transistors contain a gate terminal G, a drain terminal D, a source terminal S, and a body terminal B. As a result, there are six possible terminal-to-terminal voltages for PMOS transistor 200 and NMOS transistor 250. The six possible terminal-to-terminal voltages include a drain-to-gate voltage VDG, a drain-to-source voltage VDS, a drain-to-body voltage VDB, a gate-to-source voltage VGS, a gate-to-body voltage VGB, and a source-to-body voltage VSB.
Furthermore, when two or more of the transistor terminals are electrically connected together in an meaningful way, the number of transistor terminals will be reduced from four terminals to three terminals, or from four terminals to two terminals. As a result, the possible number of terminal-to-terminal voltage pairs will be reduced from six terminal pairs to three terminal pairs, or from six terminal pairs to one terminal pair.
The reduction in the number of terminal-to-terminal voltage pairs is illustrated in FIGS. 3A-3D and 4A-4D. FIGS. 3A and 4A show schematic diagrams that illustrate prior-art PMOS transistor 200 and NMOS transistor 250, with the body connected to the source. In this case, the source-to-body voltage VSB is zero, the gate-to-source voltage VGS and the gate-to-body voltage VGB are the same, and the drain-to-source voltage VDS and the drain-to-body voltage VDB are also the same.
FIGS. 3B and 4B show schematic diagrams that illustrate prior-art PMOS transistor 200 and NMOS transistor 250, with the gate connected to the drain. In this case, the gate-to-drain voltage VGD is zero, the drain-to-source voltage VDS and the gate-to-source voltage VGS are the same, and the drain-to-body voltage VDB and the gate-to-body voltage VGB are also the same.
FIGS. 3C and 4C show schematic diagrams that illustrate prior-art PMOS transistor 200 and NMOS transistor 250, with the body connected to the source and the gate connected to the drain. In this case, the source-to-body voltage VSB is zero, the gate-to-source voltage VGS and the gate-to-body voltage VGB are the same, and the drain-to-source voltage VDS and the drain-to-body voltage VDB are also the same. In addition, the gate-to-drain voltage VGD is zero, and the drain-to-body voltage VDB and the gate-to-body voltage VGB are the same. As a result, only one unique terminal-to-terminal voltage is present.
FIGS. 3D and 4D show schematic diagrams that illustrate prior-art PMOS transistor 200 and NMOS transistor 250, with the body connected to the source and the drain. In this case, the source-to-body voltage VSB, the drain-to-source voltage VDS, and the drain-to-body voltage VDB are all equal to zero, and the gate-to-source voltage VGS, the gate-to-body voltage VGB, and the gate-to-drain voltage VGD are all the same. As a result, only one unique terminal-to-terminal voltage is present.
During normal transistor operation, all of the terminal-to-terminal voltages shown in FIGS. 2, 3 and 4 must be kept below a maximum value, which is usually determined by the breakdown voltage of the gate oxide. (This assumes that the PN junction breakdown voltage is greater than the gate oxide breakdown voltage, which is usually the case).
Furthermore, the maximum breakdown voltage of the gate oxide has two values: a DC value and a transient value. The DC value is always lower than the transient value, mainly because the DC value causes the maximum cumulative stress on the oxide. In contrast, the transient breakdown voltage of the gate oxide is always higher than the DC value, mainly because the transient value stresses the gate oxide for a smaller percentage of the time, resulting in less cumulative stress on the oxide.
FIG. 5A shows a schematic diagram that illustrates an example of a prior-art non-inverting tristate output buffer 500. In addition, FIG. 5B shows a schematic diagram that illustrates an example of a second prior-art non-inverting tristate output buffer 550.
Referring to FIG. 5A, buffer 500 employs a single NMOS transistor N1 and a single PMOS transistor P1, to drive the buffer output VOUT. In contrast, referring to FIG. 5B, buffer 550 employs two stacked PMOS transistors P1 and P2, and two stacked NMOS transistors N1 and N2, to drive the buffer output VOUT. Because of this, PMOS transistors P1 and P2 in FIG. 5B must be made approximately twice as large (wide) as PMOS transistor P1 in FIG. 5A. Similarly, NMOS transistors N1 and N2 in FIG. 5B must be made approximately twice as large (wide) as NMOS transistor N1 in FIG. 5A.
Nevertheless, output buffer 500 contains 18 transistors, whereas output buffer 550 only contains 8 transistors. Therefore, both buffers can be made comparable, in terms of circuit performance and circuit area.